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Spanning multiple standards, frequency bands and multimedia applications, 3.5G mobile phones are becoming increasingly complex. This trend, coupled with a demand for low-cost, thin-profile handset designs, is driving the need for smaller RF subsystems. And now, with the projected growth of high-speed downlink packet access (HSDPA)-enabled networks, the requirement for higher data throughput in these subsystems is increasing as the realization of multimedia cellular applications becomes more evident.

As the demand for higher integration increases, RF integrated circuit (RFIC) designers must stretch the limits of available process technologies to implement transceiver architectures that support wideband multistandard mobile operation. Given the additional demand for smaller and cheaper solutions, it is understandable that many 3.5G RFIC designers are migrating to nanometer CMOS process technologies.

The near-term goal in CMOS integration is to create a monolithic RF transceiver that supports quad-band GSM/EDGE and multiband WCDMA operation with enhanced HSDPA performance. As RF CMOS technologies mature at deep submicron levels (90 nm and lower) it is a reasonable expectation that innovative IC designers will realize the complete integration of RF transceiver and baseband processor functionalities in a single chip. This RF-baseband integration effort is already gaining momentum for GSM/GPRS systems.

In the not-too-distant past, BiCMOS process technologies, such as silicon germanium (SiGe) and silicon-on-insulator (SOI), were more suitable for analog and RFIC design than CMOS. However, as CMOS processes continue to mature in their support of analog and RF design, they are fast becoming the technology of choice in RFIC development. This transition is driven primarily by the fact that CMOS processes are less expensive and more conducive to large-scale integration than BiCMOS.

IC designers making this transition have tended to simply transfer their analog-based bipolar-type circuit designs from BiCMOS to CMOS. The negative result of such an approach to RF CMOS design is larger die size and higher current consumption. Thus, the only benefit gained in this move to CMOS is reduced cost due to a cheaper wafer process.

A digital approach to RF design is needed to reap the full benefits of CMOS. By implementing digital-based transceiver architectures, RFIC designers take full advantage of the switching characteristics of MOS transistors in CMOS, thereby significantly decreasing size and current consumption in addition to cost. Only when such an approach to RF CMOS design is taken can Moore's law be fully leveraged.

To further illustrate the digital CMOS advantage, an analog filter circuit is more than twice the size and consumes more than twice the current than its digital equivalent at the same CMOS process node. When these filter circuits are implemented at subsequent process nodes, the size difference grows exponentially, thus demonstrating the scalable advantage of digital circuitry in CMOS.

Analog RF circuits, in general, require higher supply voltage levels than digital RF circuits to maintain similar performance levels. Supply voltages below 1.4 V (at 90 nm CMOS and smaller) are not suitable for analog RF circuits because very high current levels are needed to meet dynamic range and matching requirements. Conversely, for digital RF circuits, current consumption decreases at smaller process nodes.

As line widths continue to shrink, nanometer CMOS technology is also enabling RFIC designers to achieve ever-higher levels of integration. For example, at 130 nm line widths, it is possible to design and fully integrate digital loop filters for PLLs, which not long ago were considered a standard external bill of materials requirement for RF transceivers.

The emergence of the DigRF digital baseband interface standard has further facilitated the move toward a more digital-oriented CMOS transceiver design. The current release of the DigRF standard (version 1.12) supports the full integration of a 2.5G analog baseband processor. The next release of the DigRF standard will enable 3G analog baseband integration into the transceiver.

The above-mentioned size, current and integration differentiators demonstrate that digital-centric RF CMOS transceiver designs have a decisive long-term advantage over analog-centric designs. They will continue to decrease in cost and feature increased programmability.

It is conceivable that transceiver designs in CMOS at 65 nm line widths could become as much as 90% digital. The potential of this trend is illustrated in Figure 1. At the 65 nm CMOS process node, traditional analog circuits such as baseband filtering, transmit upconverters and PLLs will transition from the analog domain to the digital domain.

As mobile phones have incorporated support for more frequency bands and wideband modulation standards, receiver architectures have followed a progression from high intermediate frequency (IF) designs to zero-IF designs, otherwise known as direct downconversion.

Initially, high-IF super-heterodyne (super-het) receivers were used quite extensively for low-band GSM handsets. Although super-het architectures produced robust GSM receivers, they were limited in their ability to support a broad range of frequencies and required large, expensive external IF filters.

When RFIC designers started implementing quad-band (GSM850, EGSM900, DCS1800 and PCS1900) GSM and EDGE functionality into single-chip transceivers, they gravitated toward either direct downconversion or low-IF architectures, both of which eliminated the need for external IF filtering. However, in support of wideband modulation standards, such as WCDMA, low-IF architectures have fallen short, whereas direct downconversion architectures have proven ideal.

Direct downconversion receivers also feature better spurious response than low IF designs. This advantage is due to the fact that low-IF receivers have to contend with image tones, and direct downconverters, in general, display higher tolerance to spurs generated by PLLs.

When integrating a direct downconversion mixer within a proprietary digital-based receiver design, automatic calibration algorithms can be designed into the receiver itself. Calibration parameters can be programmed into the receiver during chip design validation, thereby eliminating the need for unit calibration on the handset manufacturing line.

The design of direct downconversion receivers does present its challenges. Due to their susceptibility to dc offsets at the mixer output (at baseband levels) in the presence of blockers, RFIC designers have found the application of direct downconversion architectures to narrow-band modulation schemes an arduous task. To further complicate the dc offset issue, 1/f “flicker” noise is introduced into the receiver when direct downconversion architectures are implemented in CMOS.

Innovative CMOS RFIC design techniques, which are the secret sauce of successful direct downconversion design, are required to resolve these dc offset issues. When these dc offset challenges are overcome, the benefits of direct downconversion receivers make them the clear architecture of choice for multimode transceiver design.

First-generation HSDPA-enabled networks are targeting Category 6 throughput performance, which has a 3.6 Mbps theoretical downlink data rate. The effective HSDPA data rates are dependent on the processing capabilities of the baseband processor, as well as the ability of the transceiver to receive and downconvert a high-quality RF signal throughout the cell.

In attempts to maximize effective HSDPA throughput and eliminate fading conditions across the entire cell, handset designers are beginning to implement receive diversity, which uses dual antennas and receive chains. Introducing receive diversity into Category 6 HSDPA systems greatly improves effective data rates, pushing them to maximum capacity close to the cell center. A radio subsystem that implements receive diversity using a next-generation advanced receiver can more than double the effective downlink data rate to the mobile device throughout the cell as shown in Figure 2.

The future implementation of a WCDMA digital baseband interface in RF transceivers — pending the ratification of the 3G DigRF standard — will enable the application of innovative digital filtering techniques in the receive path. The resulting digital filters will improve receiver error vector magnitude (EVM), and thereby increase HSDPA data rates.

With the emergence of new modulation standards that accommodate data transmission in cellular frequency bands, two competing transmitter architectures have surfaced: polar loop and linear (direct upconversion). There are four types of polar-loop architectures prevalent in RF transceivers today: large and small signal closed loop, as well as large and small signal open loop.

Linear transmitters directly upconvert baseband level I and Q signals to radio frequencies, and are able to use standard linear power amplifiers (PAs). Both large signal polar architectures require coupling with a custom non-linear PA to complete the loop. Both types of small signal polar transmitters complete the polar loop internally, and thus, like direct upconversion transmitters, they can use linear PAs.

The main requirements that are driving today's transmitter designs include:

• support for multiple modulation standards;
• power efficiency;
• output signal noise;
• transmit stability; and n ease of manufacturing.

Linear direct upconversion transmitters support narrowband and wideband transmission, and are proven to perform reliably in volume production of EDGE and WCDMA handsets. Large signal polar loop architectures, however, do not support wideband modulation schemes due to the limitations of today's non-linear PAs.

Currently available non-linear PAs used in large signal polar loop designs can only modulate low AM content signals, such as 8 PSK (EDGE). This constraint is due to the fact that these PAs cannot provide the peak-to-average ratios required for more complex modulations, such as the ones used for WCDMA transmission.

Small signal polar designs, on the other hand, can support modulation schemes with relatively high peak-to-average ratios. These increased peak-to-average ratios are achieved by means of developing efficient correction schemes, which also reduce the required amount of production calibration relative to large signal polar designs. Though some of these small signal polar correction schemes exist today, they consume more current and chip space than their linear counterparts.

Designers of polar loop transceivers promise higher power-added efficiency (PAE), which is a measurement of output power relative to PA current draw and supply voltage. This claim is made because, due to the relatively low output noise generated by polar loop transceivers, the PA can operate at levels that are close to saturation.

At high output power levels (> +20 dBm), the power-added efficiency (PAE) for polar loop designs is higher than that of linear designs. However, the PAE is about the same in linear and polar loop designs at lower output power levels (< +20 dBm), which is the typical output power range for WCDMA transmission.

When measuring PAE, it is important to do so over the entire output power range — not just at maximum output power levels — to take into account the current levels across the full operating range. It should also be noted that PAE is, in fact, a limited measurement of overall system power efficiency because it only takes into account the supply voltage and current draw of the PA alone.

A more comprehensive measure of system-wide transmit power efficiency is illustrated in Figure 3. Transmit power efficiency (TXE) factors in not only the PA current supply contribution, but also that of the transmitter itself, and any other miscellaneous supporting circuitry that is drawing current during transmit operation.

When TXE measurements are compared across competing architectures, linear transmitters exhibit comparable TXE to small signal and large signal open polar loop transmitters. Large signal closed polar loop designs are the least efficient due to their high-current feedback circuitry, which in some implementations, draws more than 100 mA.

It should be noted that in GSM applications, PAE approximately equals TXE because the majority of the current is drawn by the PA. However, in WCDMA applications, the PA typically operates at lower current levels in the field. In such cases, the combined baseband processor and transmitter current consumption becomes the greater contributor to the power efficiency equation. Mobile handset designers are also using novel power management techniques to further reduce system power consumption. An innovative application of dc-dc converters in WCDMA and EDGE PA designs can reduce the current consumption of the PA when operating at lower, more optimum, power levels.

Polar loop designs generally modulate low noise transmit signals and do not require external SAW filtering. On the other hand, linear transmitters use mixers that tend to generate relatively noisy output signals. As a result, linear transmitters typically require the implementation of SAW filters before the PA for low-band GSM850 and EGSM900 transmission. However, with advanced design techniques, output noise generated by linear architectures can be reduced to levels typically demonstrated by polar architectures.

Today, a SAW filter is required before the PA in all WCDMA transmitter designs. The main reason for this requirement is that the transmit noise leakage into the receive section must be 10 dB below the thermal noise level in order to maintain an acceptable receive noise floor.

The technology needed to remove this SAW filter from the WCDMA transmit chain does not solely depend upon improved transceiver design. The duplexer plays a large role in this SAW filter requirement. To compensate for the limitations of today's duplexers, which display a great deal of performance variation from unit to unit over temperature, the output phase noise of the transceiver would have to be better than -175 dBc/Hz at a 40 MHz offset in order to remove the SAW filter. All linear and polar loop transmit architectures addressed in this article are a long way away from achieving such a phase noise requirement.

Because large signal polar loop transmitters present separate amplitude and phase components of the transmit signal to the PA, precise matching is required to provide sufficient signal stability. Preventing signal delay due to phase and amplitude mismatch in polar loop designs becomes a significant calibration challenge during manufacturing and, therefore, increases costs. Closed polar loop systems relieve this problem, however, at the price of lowering the TXE.

Open polar loop designs do not require a feedback circuit. However, by not “closing” the loop, they leave the integrity of the transmit signal vulnerable to variations in temperature, output power, channel frequency and PCB layout, resulting in complex unit calibration procedures during volume manufacturing.

In attempts to provide greater PA stability, RFIC designers devoted to polar loop architectures have begun integrating the feedback loop entirely within the transceiver chip, hence the label “small signal.” This design technique enables small signal polar loop transmitters to use linear PAs. Feedback stability and signal delays resulting from phase and amplitude mismatch are still challenging issues in these designs, but they are easily mitigated because they do not have to contend with the variability introduced by non-linear PAs.

Linear transmitters offer much greater PA stability and do not require complex feedback loops because IQ amplitude and phase imbalances are adjusted on the baseband level prior to RF upconversion. Once a linear transmitter is optimized to exhibit a predictable linear gain, it can be manufactured with one-step calibration during volume production, thus lowering manufacturing costs for handset OEMs and ODMs.

Applying innovative design techniques in a 130 nm CMOS process, Sirific Wireless has successfully implemented robust direct up/downconversion architectures in its Nexus III family of single-chip RF transceivers for multiband HSDPA/WCDMA/EDGE mobile applications. The premier transceiver in this product portfolio is the SW3210 single-chip CMOS RF transceiver with multiband receive diversity. This highly integrated multiband transceiver comes in a thin 7 mm × 7 mm × 1 mm land-grid array (LGA) package.

By incorporating a 2.5 DigRF-compliant baseband interface into its Nexus III transceivers, Sirific Wireless has increased the amount of digital circuitry in its GSM/EDGE transmit and receive paths. As a result, the SW3210's GSM/EDGE receiver features increased programmable digital filtering that is significantly smaller and draws much less current than similar analog filter circuitry.

Also, it has leveraged its expertise in advanced RF CMOS design to optimize performance and resolve design issues associated with direct-conversion architectures. The result is a digital-centric direct downconversion receiver and a low-noise direct upconversion transmitter that support all narrowband and wideband modulation types.

As mentioned earlier in this article, dc offsets at the mixer output for narrowband receive signals are particularly difficult phenomena to resolve in direct downconversion design. Sirific has implemented a patented local oscillator (LO) design and programmable dc offset correction circuitry in the digital receive path to solve this problem. It has also applied advanced CMOS design techniques to mitigate 1/f noise.

With two distinct receive paths in its WCDMA receiver, the SW3120 supports full receive diversity. When matched with a dual-antenna radio front end and a baseband processor that supports HSDPA category 9 receive diversity operation, it can enable downlink data rates up to 10.2 Mbps throughout the cell.

In its linear transmit architecture, the company has significantly reduced the mixer noise for GSM and EDGE, thus eliminating the need for external SAW filters. The transceiver's transmit chain yields high TXE during GSM/EDGE transmission because current draw of the transmitter is relatively low due to the increased amount of digital CMOS circuitry.

An example of a complete tri-band WCDMA, quad-band EDGE radio subsystem with receive diversity built around the SW3210 is shown in Figure 4. This multimode radio subsystem fits into a PCB area of 6.1 cm2, and yields a bill of materials of less than 172 components, as demonstrated in the radio evaluation module shown in Figure 5. This compact radio subsystem makes the 3.5G CMOS transceiver chip suitable for mobile handsets and embedded cellular applications within data cards, PDAs and laptops.

Kiran Konanur is vice president of marketing at Sirific Wireless. He holds a Bachelor of Applied Science degree in Computer Engineering from the University of Waterloo, Canada.

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