A survey by Collet International Research showed that only 39% of designs were bug-free at first silicon while 60% contained logic or functional flaws^[2]. Detecting flaws this late in the design cycle is expensive since, according to Maxfield and Goyal, “each delay in detection and correction of a design problem makes it an order of magnitude more expensive to fix.”^[3] Using model-based design, algorithm developers, RF designers, software and hardware engineers and other development team members can cooperate to make trade offs and evaluate solutions with the goal of enhancing performance and reducing costs.

In a simplified digital radio design, the high-frequency signal received from the antenna first passes through an RF section followed by analog-to-digital conversion. In the case of a global system for mobile communications (GSM) system, the frequency of the incoming signal at this stage is around 70 MHz. This high-frequency signal then passes through a digital downconverter (DDC), which performs frequency translation and produces the corresponding baseband signal. In the case of a GSM system, the baseband frequency is around 270 kHz. The digital radio then recreates the audio signal after demodulating the baseband signal.

The digital downconverter (DDC) is a key component of a digital radio. The DDC performs the frequency translation necessary to convert the high sample rates down to lower sample rates for further and easier processing. The frequency and performance specifications of the DDC vary based on the actual application, but are invariably stringent and hard to design and implement. In this GSM example, we consider the specifications of the GrayChip GC4016 Quad DDC chip.^[4] The DDC in this implementation operates at approximately 70 MHz and must decimate the rate down to 270 kHz. Figure 3 shows a graphical representation of the out-of-band rejection mask specifications of a DDC to be used in GSM systems.

The GSM passband bandwidth of interest is 80 kHz. The GSM requirements for the overall response of the three-stage multirate filter of the DDC includes:

• decimating the input signal by 256;
• less than 0.1 dB of peak-to-peak passband ripple; and
• 18 dB of attenuation at 100 kHz.

One possible schematic representation of a GSM DDC is shown in Figure 2 and consists of a numeric-controlled oscillator (NCO) and a mixer to quadrature downconvert the input signal to baseband. The baseband signal is then low-pass filtered by a cascaded integrator-comb (CIC) filter followed by two finite impulse response (FIR) decimating filters to achieve a low sample rate of 270 kHz ready for demodulation. The final stage often includes a re-sampler, which interpolates or decimates the signal to achieve the desired sample rate depending on the application. Further filtering can also be achieved with the re-sampler.

This design concentrates on the three-stage multirate decimation filter, which includes a CIC and two decimating FIR filters. The CIC filter is suitable for this high-speed application (69.333 MHz) because of its ability to achieve high decimation factors and the fact that it's implemented without using multipliers.

The CIC in this example will perform decimation by 64. The second filter is a 21-tap CIC-compensation FIR filter (CFIR), which has an inverse-sync passband response, and decimates by two. The third-stage filter is a 63-tap FIR filter (PFIR), which ensures that the overall filter response meets the GSM spectral mask. It also decimates by two to achieve an overall decimation factor of 256.

We will now attempt to apply the model-based design methodology to design, simulate, implement and verify the DDC specified earlier.

1 2 3 Next

RSS    Save to Del.icio.us  Digg This